Difference between revisions of "FPGA"
From Steak Wiki
Jump to navigationJump to search| (5 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| − | + | FPGAs are a lot of fun. Though layout seems to get harder over time as the process nodes get smaller. | |
| − | == | + | ==Links== |
* https://www.eevblog.com/forum/microcontrollers/divide-clock-by-3-on-a-atf16v8b/ Divide by 3 hack | * https://www.eevblog.com/forum/microcontrollers/divide-clock-by-3-on-a-atf16v8b/ Divide by 3 hack | ||
* All of hamster wiki (on archive). Better save it though in case the archive goes down. | * All of hamster wiki (on archive). Better save it though in case the archive goes down. | ||
| + | ==Tips/Techniques== | ||
| + | ===Software=== | ||
| + | * Logisim is a common college-level teaching tool. It's a schematic entry for smaller Logic projects. With 'possibly' some output to FPGA IDEs. https://github.com/logisim-evolution/logisim-evolution https://logisim.app/ | ||
| − | === | + | ===Options=== |
| − | https://www.eevblog.com/forum/fpga/new-ti-tiny-plds-(tpld)/ | + | https://www.eevblog.com/forum/fpga/new-ti-tiny-plds-(tpld)/ - Trying to fill the gap "between simple logic ICs and too expensive, too large FPGA/CPLD". |
| − | |||
[[Category:online notes]] | [[Category:online notes]] | ||
Latest revision as of 05:25, 16 November 2025
FPGAs are a lot of fun. Though layout seems to get harder over time as the process nodes get smaller.
Links
- https://www.eevblog.com/forum/microcontrollers/divide-clock-by-3-on-a-atf16v8b/ Divide by 3 hack
- All of hamster wiki (on archive). Better save it though in case the archive goes down.
Tips/Techniques
Software
- Logisim is a common college-level teaching tool. It's a schematic entry for smaller Logic projects. With 'possibly' some output to FPGA IDEs. https://github.com/logisim-evolution/logisim-evolution https://logisim.app/
Options
https://www.eevblog.com/forum/fpga/new-ti-tiny-plds-(tpld)/ - Trying to fill the gap "between simple logic ICs and too expensive, too large FPGA/CPLD".