FPGA - Rotary Encoder - Revision history

ViciousCarnivore: /* Resources */

2024-04-19T22:58:49Z

Resources

Adminguy at 17:54, 13 July 2020

2020-07-13T17:54:54Z

Adminguy: /* Resources */

2020-07-06T03:40:35Z

Resources

Adminguy: /* Resources */

2020-07-06T03:40:20Z

Resources

Adminguy at 02:58, 28 October 2019

2019-10-28T02:58:12Z

Adminguy: /* Init hex File */

2019-10-28T02:57:32Z

Init hex File

Adminguy: /* Init hex File */

2019-10-28T02:55:35Z

Init hex File

Adminguy at 02:51, 28 October 2019

2019-10-28T02:51:33Z

Adminguy at 02:50, 28 October 2019

2019-10-28T02:50:31Z

Adminguy at 05:34, 18 October 2019

2019-10-18T05:34:12Z

@@ Line 1,141: / Line 1,141: @@
 * [http://papilio.cc/ Papilio FPGA] While the Papilio is obsolete now, and you should probably start with a newer FPGA, it's still not a bad place to start.
 * [http://hamsterworks.co.nz HamsterWorks]
 * [https://www.eevblog.com/forum/projects/rotary-encoders-new-polling-and-pin-interrupt-servicing-routines/ EEVblog Forum] The algorithm for the Rotary was from here.
 * [http://dangerousprototypes.com/docs/CPLD:_Complex_programmable_logic_devices#CPLD_development_tutorials] Some basic vhdl/verilog/schematic entry examples for ISE. A good place to start, although I like HamsterNZ's pdf better. Still, some good info here on setup, and initialization. Good on these gentlemen for their use of CC-0 / Public Domain.
 {{Electronics}}

← Older revision		Revision as of 17:54, 13 July 2020
Line 5:		Line 5:
	There is Rotary_Top.vhd, which is the main code, then there is rotary.vhd. Finally you will need to initialize the Block Ram, and also optionally include a init hex file.		There is Rotary_Top.vhd, which is the main code, then there is rotary.vhd. Finally you will need to initialize the Block Ram, and also optionally include a init hex file.

		+	'''Caution: Prototype code! Expect extra notes / comments.'''

	==Rotary_Top.vhd==		==Rotary_Top.vhd==

@@ Line 1,141: / Line 1,141: @@
 * [http://hamsterworks.co.nz HamsterWorks]
 * [https://www.eevblog.com/forum/projects/rotary-encoders-new-polling-and-pin-interrupt-servicing-routines/ EEVblog Forum] The algorithm for the Rotary was from here.
-* [http://dangerousprototypes.com/docs/CPLD:_Complex_programmable_logic_devices#CPLD_development_tutorials] Some basic vhdl/verilog/schematic entry examples for ISE. A good place to start, although I like HamsterNZ's pdf better. Still, some good info here on setup, and initialization. Good on these men for their use of CC-0 / Public Domain.
+* [http://dangerousprototypes.com/docs/CPLD:_Complex_programmable_logic_devices#CPLD_development_tutorials] Some basic vhdl/verilog/schematic entry examples for ISE. A good place to start, although I like HamsterNZ's pdf better. Still, some good info here on setup, and initialization. Good on these gentlemen for their use of CC-0 / Public Domain.
 {{Electronics}}

@@ Line 1,138: / Line 1,138: @@
 ==Resources==
-* [http://papilio.cc/ Papilio FPGA] While the Papilio is obsolete now, and you should probably start with a newer FPGA, it's still now a bad place to start.
+* [http://papilio.cc/ Papilio FPGA] While the Papilio is obsolete now, and you should probably start with a newer FPGA, it's still not a bad place to start.
 * [http://hamsterworks.co.nz HamsterWorks]
 * [https://www.eevblog.com/forum/projects/rotary-encoders-new-polling-and-pin-interrupt-servicing-routines/ EEVblog Forum] The algorithm for the Rotary was from here.
 {{Electronics}}

← Older revision		Revision as of 02:58, 28 October 2019
Line 1:		Line 1:
−	~~Reap what you sow.~~ Here's ~~some~~ public domain code for a Spartan 3E, to interface with multiple rotary encoders. It's currently tested up to 8. It uses Block RAM to keep track of a Rotary ID and Value for the rotary (between 0-127). It outputs the rotary values via UART on 57600 baud. Based off of the Papilio and also HamsterNZ's introductory PDF on FPGAs.	+	Here's public domain code for a Spartan 3E, to interface with multiple rotary encoders. It's currently tested up to 8. It uses Block RAM to keep track of a Rotary ID and Value for the rotary (between 0-127). It outputs the rotary values via UART on 57600 baud. Based off of the Papilio and also HamsterNZ's introductory PDF on FPGAs.

	I have different versions of this. I've had some issues with UART partial garbage output on a Spartan 3E 500, whereas the Papilio's 250 did not have such issues. I'll start with the one that's compatible with the Papilio board (including the pinout / constraints.ucf file).		I have different versions of this. I've had some issues with UART partial garbage output on a Spartan 3E 500, whereas the Papilio's 250 did not have such issues. I'll start with the one that's compatible with the Papilio board (including the pinout / constraints.ucf file).

@@ Line 1,028: / Line 1,028: @@
 ==Init hex File==
-You will also need an init Hex file to load in the Block RAM, in order to make it easy to see where the bits start and stop. This file isn't complete. It stops early, but to complete it, you would just go to 0060 or so (to reach 160 bytes). The radix is 16 (so hex) and each two integers is one byte (e.g. 0x00, 0x01, would be the first two). You would just need to either complete the rest of them. This is what the UART outputs, without any data added. So you see 00, then 01. The 01 is an index, the 00 is the value of the rotary encoder (the first one being the first encoder), and so on. This way you get the UART from FPGA to the micro with an index.
+You will also need an init Hex file to load in the Block RAM, in order to make it easy to see where the bits start and stop. The radix is 16 (so hex) and each two integers is one byte (e.g. 0x00, 0x01, would be the first two). This is what the UART outputs, without any data added. So you see 00, then 01. The 01 is an index, the 00 is the value of the rotary encoder (being 7 bits, so 0 - 127), and so on. This way you get the UART from FPGA to the micro with an index.
 It should look something like:
 <pre>
@@ Line 1,057: / Line 1,057: @@
 ,
 ,
 </pre>

@@ Line 1: / Line 1: @@
 Reap what you sow. Here's some public domain code for a Spartan 3E, to interface with multiple rotary encoders. It's currently tested up to 8. It uses Block RAM to keep track of a Rotary ID and Value for the rotary (between 0-127). It outputs the rotary values via UART on 57600 baud. Based off of the Papilio and also HamsterNZ's introductory PDF on FPGAs.
-I have different versions of this. I've had some issues with UART timing on a Spartan 3E 500, whereas the Papilio's 250 did not have such issues. I'll start with the one that's compatible with the Papilio board (including the pinout / constraints.ucf file).
+I have different versions of this. I've had some issues with UART partial garbage output on a Spartan 3E 500, whereas the Papilio's 250 did not have such issues. I'll start with the one that's compatible with the Papilio board (including the pinout / constraints.ucf file).
 There is Rotary_Top.vhd, which is the main code, then there is rotary.vhd. Finally you will need to initialize the Block Ram, and also optionally include a init hex file.

← Older revision		Revision as of 02:50, 28 October 2019
Line 1,064:		Line 1,064:
	* [http://hamsterworks.co.nz HamsterWorks]		* [http://hamsterworks.co.nz HamsterWorks]
	* [https://www.eevblog.com/forum/projects/rotary-encoders-new-polling-and-pin-interrupt-servicing-routines/ EEVblog Forum] The algorithm for the Rotary was from here.		* [https://www.eevblog.com/forum/projects/rotary-encoders-new-polling-and-pin-interrupt-servicing-routines/ EEVblog Forum] The algorithm for the Rotary was from here.
		+
		+	{{Electronics}}

← Older revision		Revision as of 05:34, 18 October 2019
Line 970:		Line 970:

	</pre>		</pre>
		+
		+	==Constraints/Pin Mapping==
		+	For Papilio FPGA.
		+	<pre>
		+	NET ROT(0) LOC="P16" \| IOSTANDARD=LVTTL;
		+	NET ROT(1) LOC="P17" \| IOSTANDARD=LVTTL;
		+	#NET ROT2(0) LOC="P12" \| IOSTANDARD=LVTTL;
		+	#NET ROT2(1) LOC="P15" \| IOSTANDARD=LVTTL;
		+	NET TX(0) LOC="P12" \| IOSTANDARD=LVTTL;
		+	#NET RX(0) LOC="P15" \| IOSTANDARD=LVTTL;
		+	NET LED(0) LOC="P2" \| IOSTANDARD=LVTTL;
		+	NET LED(1) LOC="P3" \| IOSTANDARD=LVTTL;
		+	NET LED(2) LOC="P4" \| IOSTANDARD=LVTTL;
		+	NET LED(3) LOC="P5" \| IOSTANDARD=LVTTL;
		+	NET LED(4) LOC="P98" \| IOSTANDARD=LVTTL;
		+	NET LED(5) LOC="P95" \| IOSTANDARD=LVTTL;
		+	NET LED(6) LOC="P94" \| IOSTANDARD=LVTTL;
		+	NET LED(7) LOC="P92" \| IOSTANDARD=LVTTL;
		+	# no tabs? spaces only?
		+	NET clk LOC="P89" \| IOSTANDARD=LVCMOS25;
		+	#NET LEDWATCH(0) LOC="P58" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(1) LOC="P54" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(2) LOC="P41" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(3) LOC="P36" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(4) LOC="P34" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(5) LOC="P32" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(6) LOC="P25" \| IOSTANDARD=LVTTL;
		+	#NET LEDWATCH(7) LOC="P22" \| IOSTANDARD=LVTTL;
		+	#NET DATAOUTUART LOC="P91" \| IOSTANDARD=LVTTL;
		+	NET ROT2(0) LOC="P22" \| IOSTANDARD=LVTTL;
		+	NET ROT2(1) LOC="P18" \| IOSTANDARD=LVTTL;
		+	NET ROT3(0) LOC="P25" \| IOSTANDARD=LVTTL;
		+	NET ROT3(1) LOC="P23" \| IOSTANDARD=LVTTL;
		+	NET ROT4(0) LOC="P32" \| IOSTANDARD=LVTTL;
		+	NET ROT4(1) LOC="P26" \| IOSTANDARD=LVTTL;
		+	NET ROT5(0) LOC="P34" \| IOSTANDARD=LVTTL;
		+	NET ROT5(1) LOC="P33" \| IOSTANDARD=LVTTL;
		+	NET ROT6(0) LOC="P36" \| IOSTANDARD=LVTTL;
		+	NET ROT6(1) LOC="P35" \| IOSTANDARD=LVTTL;
		+	NET ROT7(0) LOC="P41" \| IOSTANDARD=LVTTL;
		+	NET ROT7(1) LOC="P40" \| IOSTANDARD=LVTTL;
		+	NET ROT8(0) LOC="P54" \| IOSTANDARD=LVTTL;
		+	NET ROT8(1) LOC="P53" \| IOSTANDARD=LVTTL;
		+	</pre>
		+

	==Block RAM Settings==		==Block RAM Settings==